1. Field of the Invention
The present invention generally relates to a method of making independently optimized P and NFET devices with different gate lengths by SIT technique. The invention directly modifies the spacer width without the need for added resist etch processes.
2. Description of the Related Art
As the industry pushes integrated circuit chip performance, the device gate length is being reduced to about half of the minimum lithographic dimension, and is still shrinking. Such sublithographic gate dimensions are achieved by trimming the etching mask (either hard mask or photoresist) of the gate material before the gate material etch. However, the tolerance of this method is inherently unstable because of the difficulty in controlling the photolithography and etch dimensions, as well as the trim dimension.
Sidewall image transfer (SIT) has been known to produce FET devices of sublithographic dimensions with superior gate length control. However, each SIT process only produces one sublithographic gate length, which is a serious shortcoming of this technique since PFET and NFET device require different gate widths to optimize both PFET and NFET device performance. In order to independently adjust the width of these features with SIT, an additional resist apply, expose, and etch process is needed to trim the spacers to a smaller width where desired, or to form an additional spacer where desired in order to widen some patterns. The invention described below addresses these needs.